library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lab4 is 
port(
	KEY : in std_logic_vector(3 downto 0);
	SW : in std_logic_vector(17 downto 0);
	LEDG : out std_logic_vector(7 downto 0);
	LEDR : out std_logic_vector(17 downto 0)
);
end lab4;
  
architecture behaviourial of lab4 is

	-- Component declaration for the processor entity
	component processor is
	port(
		clk, reset : in std_logic;
		instruction_in: in std_logic_vector(15 downto 0);
		get_next_instruction: out std_logic;
        	datapath_out: out std_logic_vector(7 downto 0)
       	);
	end component;

	-- Some internal signals
	signal clk, reset, get_next_instruction : std_logic;
	signal instruction_in : std_logic_vector(15 downto 0);
	signal datapath_out : std_logic_vector(7 downto 0);

begin

	-- Instantiate a processor entity
	u0 : processor 
	port map(
		clk => clk,
		reset => reset,
		instruction_in => instruction_in,
		get_next_instruction => get_next_instruction,
		datapath_out => datapath_out
	);

	-- Now connect these internal signals to the correct inputs and outputs
	clk <= KEY(0);
	reset <= KEY(3);
	instruction_in <= SW(15 downto 0);
	LEDR(0) <= get_next_instruction;
	LEDG(7 downto 0) <= datapath_out;

end behaviourial;

     
